Joshua or Cyrix MIII
Cyrix was working on a brand new processor nucleus (code name Jalapeño) before the company was sold to VIA. The processor was expected to be marketed in the MIII in the middle of year 2000, but I do not know what happened to the design.
The features were:
Clock frequencies starting at 533 MHz (PR533).
Built in 64 KB L1 cache, which works at full clock speed.
Built in 256 KB L2 cache, which works at full clock speed.
Built in 3DNow! 3D graphics acceleration.
Socket 370 with 133 MHz bus for RAM.
From the original MIII design the following rests: Built in hardware coder for MPEG. Use of Direct RDRAM (Rambus RAM). Powerful memory controller, which should permit transmission at 3.2 GB per second.
VIA3 later introduced a Cyrix III processors based on IDT's WinChip technology.
Compared to Athlon
Joshua was not a high end processor like AMD’s K7 Athlon. However it
is intended to be a powerful low price CPU with integrated sound and graphics
controller. If we compare the design with the Athlon, we see a slightly lower
|Number of program instructions
which can be
|Number of internal
operations per clock cycle
|Pipelines to floating-point number operations
(FP, MMX, 3DNow!)
Read about chip sets on the motherboard in module
Read more about RAM in module 2e
Read module 5a about expansion cards, where
we evaluate the I/O buses from the port side.
Read module 5b about AGP and module
5c about Firewire.
Read module 7a about monitors, and 7b
on graphics card.
Read module 7c about sound cards, and 7d
on digital sound and music.
Copyright (c) 1996-2005 by Michael B. Karbo. www.karbosguide.com.