Karbosguide.com - Module 3e.12

The VIA "Joshua" processor

The contents:

An introduction
Compared to Athlon

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Cyrix was working on a brand new processor nucleus (code name Jalapeño) before the company was sold to VIA. The processor was expected to be marketed in the MIII in the middle of year 2000, but I do not know what happened to the design.
The features were:

Clock frequencies starting at 533 MHz (PR533).
Built in 64 KB L1 cache, which works at full clock speed.
Built in 256 KB L2 cache, which works at full clock speed.
Built in 3DNow! 3D graphics acceleration.
Socket 370 with 133 MHz bus for RAM.
From the original MIII design the following rests: Built in hardware coder for MPEG. Use of Direct RDRAM (Rambus RAM). Powerful memory controller, which should permit transmission at 3.2 GB per second.

VIA3 later introduced a Cyrix III processors based on IDT's WinChip technology.

Compared to Athlon

Joshua was not a high end processor like AMD’s K7 Athlon. However it is intended to be a powerful low price CPU with integrated sound and graphics controller. If we compare the design with the Athlon, we see a slightly lower performance:

Joshua or Cyrix MIII

Joshua Athlon

Number of program instructions
which can be executed superscalar
(simultaneously) 2 3

Number of internal
operations per clock cycle 6 9

Pipelines to floating-point number operations
(FP, MMX, 3DNow!) 2 3

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Read about chip sets on the motherboard in module 2d

	Joshua	Athlon
Number of program instructions which can be executed superscalar (simultaneously)	2	3
Number of internal operations per clock cycle	6	9
Pipelines to floating-point number operations (FP, MMX, 3DNow!)	2	3